Yan Xu
PhD Student
Hunan University
Research Interests
About
Hi, I'm a Ph.D. student in the College of Semiconductors at Hunan University.
My research focuses on hardware accelerators for cryptography and photonic-electronic architecture design. I’m working on building efficient and secure chips and hardware systems for next-generation applications. I'm also interested in creating and testing hardware security primitives, especially for protecting data in new technologies like the Internet of Things (IoT) and large AI models.
I really enjoy working across different fields. I'd love to chat and collaborate with people in cryptography, digital circuit design, large language models, and AI. I'm also excited to connect with students and researchers from areas like automotive tech, agriculture, or biomedicine—Let's team up and explore together how hardware security can help in new and unexpected ways.
Feel free to reach out—I'm always open to new ideas and collaborations!
Selected Publications
View All →Auto-Mult: A Self-Optimizing Integer Multiplier via Hybrid Decomposition and Automated Parameter Search
Yan Xu, Jianbo Guo, Mengquan Li, Hao Xiao
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Auto-Mult is a self-optimizing integer multiplier using hybrid decomposition and automated parameter search, targeting FPGA-based cryptographic hardware accelerators.
HyperNTT: An Ultra-High Throughput Number Theoretic Transform Accelerator for FHE (Accepted)
Yan Xu, Xiyan Dong, Jiarui Wang, Leyan Zhang, An Wang, Xinghua Wang, Liehuang Zhu, Jingqi Zhang
IEEE International Symposium on Circuits and Systems (ISCAS)
An ultra-high throughput NTT accelerator for FHE with conflict-free dataflow and FPGA-optimized Montgomery reduction.
PhotoMT: Accelerating Zero-Knowledge Proofs with a Photonic-Electronic Merkle Tree Engine (Accepted)
Yan Xu, Mengquan Li, Shu Li, Zhaoyuan Zhang, Kenli Li
The 63nd ACM/IEEE Design Automation Conference (DAC)
A photonic-electronic collaborative Merkle tree engine for ZKP acceleration, achieving up to 20.5× throughput improvement over ASIC designs.
Safe-IoT: A Memory-Efficient HW/SW Co-Designed ML-DSA Accelerator for IoT Edge Devices (Accepted)
Yan Xu, Jingqi Zhang, Mengquan Li, Xinghua Wang, An Wang, Liehuang Zhu
The 63nd ACM/IEEE Design Automation Conference (DAC)
A memory-efficient HW/SW co-designed ML-DSA accelerator for IoT edge devices, featuring MI-NTT and LUT-based modular multiplier.
Meta: A Memory-Efficient Tri-Stage Polynomial Multiplication Accelerator Using 2D Coupled-BFUs
Yan Xu, Ling Din, Penggao He, Zhaolun Lu, Jiliang Zhang
IEEE Transactions on Circuits and Systems I: Regular Papers
Built on FPGA, Meta provides specialized hardware acceleration for cryptographic operators, with optimized support for NIST-standardized post-quantum algorithms.
News
Just launched my corner of the web — my personal homepage! 🎉